ECE2072:A Counter that Produces an Output Every Clock Cycle - Engineering Assignment Help

Assignment Task:

Task:

Problem Description
Design a counter that produces an output every clock cycle. The output sequence that each student downloads from Moodle contains 18 Binary Coded Decimal (BCD) digits that are unique to each student. Let’s call these output values V0, V1, V2, .. V17. The count sequence wraps around from V17 back to V0. Here is the normal count sequence:

V0 V1 V2 V3 V4 V5 ...V17 V0 V1 V2 V3 V4 V5 ....

Question 1
Download from Moodle your Verilog template file named assignID.v that defines your count sequence V0 V1 V2 V3 V4 V5 ...V17 . Note that ID in assignID.v is your 8 digit ID number. This particular file must be used for your HDL code to solve the above counter problem. Complete the modules CounterSkipReverse, StateToCountSequence and CompleteCounter. The file assignID.v must not be shared with, or shown to anyone else. Do not delete lines in this file since this may invalidate your answer during a preliminary automatic compilation, marking, plagiarism and collusion checking phase. Manual marking and checking will be used after this. Download a new copy from Moodle if you accidently delete lines.
 

Question 2
In your assignID.v file complete the testbench module AssignmentTestBench that enables ModelSim to check the correct functionality of your HDL design. Ensure that you test every transition from every valid state of your circuit. Since we have a reset action, we are not testing for self-starting here. Include up to four screen captures from ModelSim showing the testbench simulation with inputs, outputs and state of your design. Use appropriate display options to maximise readability.

Question 3
Minimise the number of Logic Cells that your design requires after a synthesis compilation in Quartus with DE2 board settings. This will involve exploring different implementation strategies, checking them with your testbench and synthesising them in Quartus.

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