Simulator for Out-of-Order Processor Supporting Speculative Execution Using Register Renaming Assignment

Assignment Task

Project Description

This project requires you to implement a simulator for an out-of-order processor implementing an APEX-like ISA with an issue queue, a load-store queue and a reorder buffer that uses register renaming. The instructions are similar to the ones in Project 2, but BN and BNN are excluded for this project. The datapath of the processor to be simulated is shown on the following page.

Questions 

 1. The project specs says: “When two or more instructions that require the same function unit become ready to issue in the same cycle, the earliest dispatched instruction has the (highest) priority for using the FU”. Does this mean we limit ourselves to a total issue rate of one instruction per cycle at most for the entire processor?

 2. The test case, the architectural register file values appear in the next cycle. This seems to be a contradiction. What is the correct thing to do?

 3. In the project description the MAU is described as having two separate stages, and my understanding of this would be that a consecutive set of two memory instructions that do not depend on each other would be allowed to occupy each of the stages separately similar to the CPU pipeline. However, in test case 2 there is only one MAU stage that takes two cycles to complete allowing for only one instruction at a time. I was just wondering which of these two cases we should be implementing?

4. How are the calculated addresses passed on to the respective control flow instructions?

5. What is the role of the BFU for a JALR or JUMP instruction? 

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