EN0720 : Digital Design Automation - Modelling & Simulation of XADC - Engineering Assignment Help

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Task:

Digital Design Automation — EN0720 (KD7020) Assignment 2 2020-21 Modelling and Simulation of XADC input circuitry using the SMASH@ mixed-signal simulator Objective: • Perform and evaluate analogue simulations of the XADC® input circuitry using a mixed-signal simulator Learning Outcomes See Assignment Specification document

Figure 2.1 shows the equivalent circuitry of the Xilinx 7-series FPGA Analogue-to-Digital Converter  (XADC) auxiliary inputs. The circuitry enclosed inside the dotted box is integral to the FPGA  device, the terminal labeled ‘VA1’ represents an auxiliary input ‘VAUXP’ (‘VAUXN’ is assumed to be at ground potential). 

The components labeled ‘XSW1..3’ (XADC_SW) are analog switches controlled by digital signals ‘cap_sample’ and ‘cap_reset’.  

When the XADC is acquiring a new sample value, ‘cap_sample’ is at logic-1 and switches XSW1  and XSW2 are closed, the signal ‘cap_reset’ is at logic-0 and switch XSW3 is open. The storage capacitance ‘Xcap’ charges up to the current input voltage during the time interval known as the acquisition-time ‘Tack’. 

Once the storage capacitor charges up to the sample voltage, all switches are opened and the voltage across ‘Xcap’ is held constant while the analog-to-digital process takes place during the  ‘hold’ time ‘Thorold’. 

At the end of the hold-time, the storage capacitor is discharged to zero volts by closing switch  ‘XSW3’.  

The sequence repeats at intervals of time known as the sample-time ‘Tsample’. 

Appendix A provides a partial source listing for the top-level Verilog-AMS net-list description (Test_XADC_input.nsx) equivalent to the circuitry of figure 2.1. This incomplete file is also provided on eLearning, along with the source files for all sub-components. The ‘nsx’ file is compatible with the SMASH® simulation tool. 

Task 2.1 – Open the ‘Test_XADC_input.nsx’ file using a suitable text editor (such as Notepad++)  and complete the description, with the aid of figure 2.1. Initially, omit components R1 and CA (by commenting out), and comment out the pulse voltage source ‘VP1’.

Task 2.3 – Zoom in to the waveform traces to see the detail around a single ‘cap_sample’ pulse.  Estimate the time it takes for the storage capacitor to acquire the sample value. Capture the waveform view and insert it into your report with a suitable caption. 

Zoom out to an area enclosing two consecutive ‘cap_sample’ pulses. Use the zoom tool to get a  closer view of the vertical change in the voltage across the storage capacitor. Capture the waveform view and insert it into your report, adding a comment suitable caption. Briefly explain the change in the storage capacitor voltage, during the holding interval. 

Task 2.4 – Uncomment resistor R1 in the net-list description of figure 2.1. Given that the required input voltage range of the XADC is 0.0 to 1.0 volts, estimate a suitable value for R1 and rerun the transient simulation. Include the value of resistor R1 in your report. Capture the full extent of the waveform view and insert it into your report, adding a comment and suitable caption. 

Task 2.5 – Task 2.1 specifies the sample interval time as Tsample = 10us. Estimate a suitable value for the low-pass filter capacitor ‘Ca’, in the net-list. For the purposes of estimating the value of Ca, the effect of the XADC input circuitry can be neglected. 

Add the capacitor ‘Ca’ to the net-list and rerun the transient simulation. Capture the full extent of the waveform view and insert it into your report, adding a suitable caption. Briefly comment on the effect on the results of inserting the low-pass filter capacitor. 

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