Designing D-Flip-Flops Low Voltage High Speed and Near-Full Swing

Assignment Task

Design all the following D-flip-flops (D-FF). The D-FF must meet the following.

1. Vdd≤1.8V, Both Q and Q_not must be obtained.

2. For 5000 level students: Clk and input D must be at least 1.5GHz

3. For 6000 level students: Clk and input D must be at least 1.8GHz

4. Near-Full swing should be achieved i.e., Vlow = ~0V, Vhigh = ~1.8V, at output

Questions

1. Pass transistor-Based

2. Semi dynamic edge-triggered flip-flop

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