Derive the VHDL Code of the Control Circuit - Engineering Assignment Help

Assignment Task :

A stack is a buffer in which the data is stored and retrieved in first-in-last-out fashion. In a synchronous stack, it should consist of the following I/O signals:

·   w_data andr_data:  data to be written (also known as pushed) into and read (also known as popped) from the stack.

·   push and pop: control signals to enable the push or pop operation.

·   full and empty: status signals.

·   clk and reset: the clock and reset signals.

We can use a register file to construct this circuit by following the design approach of the FIFO buffer.

·      Draw a top-level diagram similar to that in Figure 9.13 (see page 282 of the Pong P.Chu. RTL Hardware Design using VHDL, Coding for Efficiency, Portability, and Scalability, John Wiley & Sons, Inc., 2006.)

·      Consider a stack of four words. Derive the VHDL code of the control circuit.

• Simulate your design with the Modelsim simulator to verify correct functioning for several typical values of the input.

  Your report should contain: the conceptual diagram of the entire design, the VHDL code and the simulation results.

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