Asynchronous Serial  Data Transmitter and Receiver - Engineering Assignment Help

Assignment Task :

 Objectives: 

• To create SystemVerilog (SV) design source descriptions for the various component parts  of a Monitoring System comprising an Analogue-to-Digital Converter, Asynchronous Serial  Data Transmitter and Receiver along with a display. 

• To incorporate an IP (Intellectual Property) module into the design using customisation and  interfacing. 

• To perform simulations of individual design modules using SV test-modules and the  Vivado® Simulator. 

• To perform simulations of the complete Monitoring System top-level module using a SV  test-module and the Vivado® Simulator. 

Assignment 1 - Description of the Monitoring System 

Figure 1, below, shows a simplified block diagram of the Monitoring System and figure 2 shows  the corresponding physical layout of the Basys3 development board. 

The system is driven by a 100MHz crystal clock and an active-high reset push button, when the  latter is pressed, the entire system is reset. The main functional blocks that make up the system  are shown in figure 1: 

i. XADC – built-in Analogue-to-Digital Converter that can be instantiated from the IP library.  The analogue input voltage range is 0.0 to +1.0 Volts. 

ii. XADC Controller – responds to manual or timer generated pulses initiating an ADC  conversion, it produces the required control signals for the XADC and interfaces with the  transmitter. 

iii. Transmitter – after each conversion, the 12-bit result is transmitted over an asynchronous  serial data link as an individual character. 

iv. Receiver – receives the asynchronous character from the transmitter and displays the value  on the 7-segment display. 

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